1. Field of the Invention
The present invention relates to a voltage rectifying and smoothing circuit for use in a regulated power supply circuit which converts an alternating current (ac) voltage to a constant direct current (dc) voltage.
2. Description of Related Art
FIG. 1 is a block diagram of a regulated power supply circuit used commonly, which converts an ac voltage to a constant dc voltage. FIGS. 2A through 2E respectively show waveforms of voltages appearing at various parts of the regulated power supply circuit. As shown in FIG. 1, the regulated power supply circuit is constituted by a transformer 10, a full-wave rectifying circuit 20, a voltage smoothing circuit 30 and a regulator circuit 40. When an ac voltage is supplied to input terminals of the primary winding Ti of the transformer 10, an ac signal having a maximum amplitude voltage of .+-.24 Volts (hereinafter simply indicated as V) for example, as illustrated in FIG. 2A is generated at the secondary winding of the transformer 10, and supplied to input terminals A(+) and B(-) of the full-wave rectifying circuit 20. Four diodes 21 through 24 are connected to the full-wave rectifying circuit 20. When a load (capacitor 31) is not connected to the the full-wave rectifier circuit 20, the ac signal shown in FIG. 2A is rectified and a full-wave rectified voltage consisting only of waveform portions of the positive polarity as illustrated in FIG. 2B is produced. In the following description, one of the output terminals is referred to as A(+) terminal, and the other of the terminals is referred to as B(-) (ground) terminal.
When the smoothing circuit 30 made of the capacitor 31 is connected across the A(+) and B(-) terminals of the full-wave rectifier circuit 20, the the capacitor 31 is charged by the full-wave rectified voltage, and a discharge of the capacitor 31 takes place by the load such as the regulator circuit 40, so that a dc voltage including an amplitude fluctuation as shown in FIG. 2C will be generated. The dc voltage shown in FIG. 2C is supplied to the regulator circuit 40 of the next stage. The source of a P-channel MOS FET 41 (hereinafter abbreviated as FET) is connected at an A(+) terminal of the regulator circuit 40, and the drain of the FET 41 is connected to a C(+) terminal of the regulator circuit 40 which functions as its output terminal. A bias resistor 42 is connected across the source and gate of the EFT 41, and the gate is connected to an output terminal of an operational amplifier 43.
Across the non-inverting input terminal (-) of the operational amplifier 43 and the ground terminal, a Zener diode 45 and a capacitor 46 are connected in parallel. Since a bias current from the source of the FET 41 is supplied to the cathode of the Zener diode 45 through a resistor 44, a stable breakdown voltage of the Zener diode 45 is supplied to the inverting input terminal of the operational amplifier 43 as a reference voltage of 6 V. The non-inverting input terminal of the operational amplifier 43 is connected to a node between a resistors 47 and 48 which are connected across the drain of the FET 41 and the ground terminal.
The operation of this regulated power supply circuit will be explained with reference to FIG. 1 and FIGS. 2A through 2E.
The dc voltage having the amplitude fluctuation generated at the A(+) terminal of the full-wave rectifier circuit 20 (shown in FIG. 2C and its voltage level is assumed to be around 24 V) is supplied to the source terminal of the FET 41. Since the resistor 42 is connected across its source and gate, the FET 41 is put in an OFF (shut-off) state, so that the voltage at its drain is 0 Volt.
Since the voltage applied at the source of the FET 41 flows into the Zener diode 45 through the resistor 44, the voltage of 6 V, that is the breakdown voltage of the Zener diode 45, is produced and supplied to the inverting input terminal of the operational amplifier 43.
The voltage at the non-inverting input terminal (+) of the operational amplifier 43, which is supplied from the node between the resistors 47 and 48 connected across the drain and the ground terminal, is equal to 0 Volt because the voltage at the drain is 0 Volt.
Consequently, the voltage at the output terminal of the operational amplifier 43 temporarily assumes a low level (almost 0 Volt), and lowers the voltage at the gate of the FET 41 towards 0 Volt. As a result, the voltage at the gate of the FET 41 becomes lower than the voltage at its source, so that the FET 41 is put in an ON (conductive) state. Thus, a rising voltage shown in FIG. 2C is issued at the drain. The voltage developed at the drain is divided by the resistors 47 and 48, and in turn supplied to the non-inverting input terminal (+) of the operational amplifier 43. If, for example, the resistance values of the resistors 47 and 48 are made equal to each other, almost a half of the voltage produced at the drain is supplied to the non-inverting input terminal of the operational amplifier 43. As explained above, the reference voltage of 6 V is supplied to the inverting input terminal (-) of the operational amplifier 43.
Since the operational amplifier 43 operates to multiply a voltage corresponding the difference between voltages at its non-inverting input terminal (+) and inverting input terminal (-) by a value corresponding to its gain, the output electric potential of the operational amplifier 43 changes to a high voltage. The control system of the regulator circuit 40 which is constituted by the output terminal of the operational amplifier 43, the gate and the drain of the FET 43, and the non-inverting input terminal of the operational amplifier 43, is made stable when the voltage of almost 6 V is supplied to the non-inverting input terminal (+) of the operational amplifier 43, in other words, when the electric potential at the drain has assumed almost 12 V.
Consequently, a dc voltage whose level is fixed at almost 12 V (whose waveform is shown in FIG. 2D) can be obtained as the output voltage of the regulator circuit 40. When the maximum amplitude value of the ac current has exceeded .+-.24 V due to a fluctuation of the maximum amplitude value, the voltage at the source of the FET 41 goes high, to to raise the drain voltage also. Therefore, the voltage at the non-inverting input terminal of the operational amplifier 43 becomes higher than the voltage at its inverting input terminal (-), and the output voltage of the operational amplifier 43 is raised again, and a stable state is attained when the output voltage is at 12 V. As described above, the regulated power supply circuit functions as a circuit for converting an ac signal to a dc signal, and obtaining a substantially constant dc voltage against the fluctuation of the ac signal.
Incidentally, the electric power consumption of the FET used in the regulator circuit 40 can be calculated by multiplying a voltage corresponding to the difference between the voltages at the source and the drain (the area P.sub.1 indicated by oblique lines in FIG. 2E) by the drain current (load current). Specifically, in the case of the regulator circuit 40 of this type of configuration, since the drain voltage is almost 12 V, the electric power consumption (Wa) of the FET 41 is expressed by the equation of: EQU Wa=(24V-12V).times.Id
where Id represents the drain current when a load is connected to the C(+) terminal of the regulator circuit 40.
Since the electric power consumption of the FET constitutes a substantial part of the electric power consumption of the regulator circuit 40, it is necessary to provide the FET 41 with a radiator of large size. Furthermore, although it is necessary that the voltage between its source and drain be set at a low level in order to reduce the electric power consumption of the FET 41, it will lead to a loss of freedom in designing especially in such cases that regulator circuit is used in an equipment for which the ac voltage being supplied or the dc voltage to be produced is minutely specified.